High Performance Elliptic Curve Point Operations

This paper studies the effect of high performance pipelined GF(2 256 ) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2 m ) normal basis multiplier for 160 ≤ m ≤ 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipelined multipliers. The proposed pipelined architecture has been shown to have a significant improvement in throughput allowing a single 3-stage pipelined multiplier to have higher throughput than an architecture employing three parallel non-pipelined multipliers. The AT 2 performance metric has shown an even more significant improvement.